This application claims priority to Korean Patent Application No. 2004-41678, filed on Jun. 8, 2004, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates generally to memory devices, and more particularly to reducing resistance of a word line in a current path of an accessed memory cell.
2. Description of the Related Art
A PRAM (Phase-change Random Access Memory) device is being developed as one of the next-generation memory devices for higher performance and lower power consumption. A PRAM device is a nonvolatile memory device for storing data by using a phase change material such as GexSbyTez (hereinafter referred to as ‘GST’).
The resistance of the phase change material is controlled by changing the state of the phase change material to be amorphous or crystalline. Such a state may be controlled by temperature adjustment. The phase change material has higher resistance when in the amorphous state and has lower resistance when in the crystalline state.
When the phase change material is “RESET”, the phase change material is changed from a crystalline state to an amorphous state. On the other hand, when the phase change material is “SET”, the phase change material is changed from an amorphous state to a crystalline state.
For adjusting temperature, a laser beam may be used. Alternatively, joule heating is generated by applying current to a heater. In the case of joule heating, current density and the time period of current application through the heater determines the amount of heat generated for controlling whether the phase change material is crystallized or becomes amorphous. In any case, the phase change material stores bit information with such two distinct crystalline and amorphous states within a memory device.
FIG. 1 shows a memory cell for a diode type of PRAM device. Referring to FIG. 1, the memory cell includes a diode D1 and a variable resistor element GST. The diode D1 is coupled between a word line WL and the variable resistor element GST. In FIG. 1, a cathode of the diode D1 is coupled to the word line WL, and an anode of the diode D1 is coupled to one end of the variable resistor element GST. Another end of the variable resistor element GST is coupled to a bit line BL. The variable resistor element GST is comprised of a phase change material.
FIG. 2 shows a circuit diagram of a conventional PRAM device comprised of an array of memory cells, with each memory cell similar to FIG. 1. Referring to FIG. 2, the PRAM device includes a word line driver 20, a plurality of word lines WL0, WL1 and WL2, an array of memory cells 10, and a plurality of bit lines BL0, BL1, . . . , BLk-1 and BLk.
Further referring to FIG. 2, the memory cells in a same row are coupled to a same one of the word lines WL0, WL1 and WL2. The memory cells in a same column are coupled to a same one of the bit lines BL0, BL1, . . . , BLk-1 and BLk.
For driving each word line, the word line driver 20 includes a respective NOR gate 22 and a respective inverter comprised of an NMOS transistor 26 and a PMOS transistor 24. The output of the respective NOR gate 22 generates a signal for providing a path of current 40 through the respective inverter with the path of current 40 also being through an accessed memory cell 10 and the bit line BLk of the accessed memory cell 10.
Operation of the PRAM device of FIG. 2 is now described. For accessing the example memory cell 10, a corresponding column selection signal Yk among column selection signals Y0, Y1, . . . , Yk-1 and Yk is enabled. The memory cell 10 is accessed for performing any of typical operations such as a read or write operation on the memory cell 10. A column selection transistor controlled by the enabled column selection signal Yk applies current 40 to the accessed memory cell 10. Such a current 40 is applied from a (write driver)/SA(Sense Amplifier) 30 to the accessed memory cell 10 via the bit line BLk.
The word line driver 10 processes an address signal GWLb and a block selection signal SiEib to couple a word line WL0 for the accessed memory cell 10 to a ground node. Thus, the word line WL0 and the ground node become within a current path 40 for the current flowing through the accessed memory cell 10.
The level of current 40 flowing through the accessed memory cell 10 depends on the resistance of the variable resistor element GST1 within the accessed memory cell 10. If the phase change material of the variable resistor element GST1 has a ‘reset’ state, the variable resistor element GST1 has a high resistance for a lower level of current 40 flowing through the accessed memory cell 10. On the other hand, if the phase change material of the variable resistor element GST1 has a ‘set’ state, the variable resistor element GST1 has a low resistance for a higher level of current 40 flowing through the accessed memory cell 10. Such variable current levels indicate the bit information stored within the memory cell 10.
In the PRAM device of the prior art in FIG. 2, the length of each of the word lines W0, WL1 and WL2 is relatively long. For example, each of the word lines W0, WL1 and WL2 may run through a row of memory cells disposed within multiple blocks of memory cells. With such a long word line WL0, current flowing through the accessed memory cell 10 is reduced by word line resistance R_wl. Such reduced current may result in an erroneous read/write operation for the accessed memory cell 10.
To solve such a problem, the main array of memory cells has been divided into a plurality of blocks having less memory cells. In the prior art, a word line driver similar to the word line driver 20 of FIG. 2 is fabricated for each such block, for reducing a word line resistance. However, a large number of the word line drivers are used with each block having a separate word line driver implemented with logical gates such as an inverter, a NAND gate, and/or a NOR gate. Such a large number of word line drivers disadvantageously occupy a large layout area.